Designing a cache using an LRU-LFU array

ABSTRACT

A system, computer program product and method for designing a cache. A server in a network system, e.g., file system, database system, may receive requests forming a workload. A trace may be performed on the workload to provide information such as the frequency count for each Logical Block Address (LBA) requested in the workload. The trace may then be analyzed by grouping the LBA&#39;s with the same frequency count and determining the number of groups counted in the trace. Upon analyzing the trace, an LRU-LFU cache may be designed. An LRU-LFU cache may comprise one or more stacks of cache entries where the number of stacks corresponds to the number of frequency groups counted in the trace. Each particular stack may then have a length based on the number of logical addresses with the same frequency count associated with that particular stack.

CROSS REFERENCE TO RELATED APPLICATION

[0001] The present invention is related to the following U.S. PatentApplication which is incorporated herein by reference:

[0002] Ser. No. ______ (Attorney Docket No. RSP920010002US1) entitled“Designing a Cache with Adaptive Reconfiguration” filed ______.

TECHNICAL FIELD

[0003] The present invention relates to the field of cache design, andmore particularly to designing a cache using a Least Recently Used(LRU)—Least Frequently Used (LFU) array thereby improving theperformance of the cache.

BACKGROUND INFORMATION

[0004] A network server, e.g., file server, database server, web server,may be configured to receive requests from clients in a network systemto read from or write to a disk, e.g., disk drive, in the networkserver. These requests may form what is commonly referred to as a“workload” for the network server. That is, a workload may refer to therequests that need to serviced by the network server.

[0005] Typically, a server in a network system comprises a disk adapterthat bridges the disk, e.g., disk drive, to the processing unit of theserver unit. A server may further comprise a cache commonly referred toas a disk cache within the disk adapter to increase the speed ofaccessing data. A cache is faster than a disk and thereby allows data tobe read at higher speeds. Thus, if data is stored in the cache it may beaccessed at higher speeds than accessing the data on the disk.

[0006] There have been many methods in designing disk caches that seekto increase the cache hit rate thereby improving performance of the diskcache. A “cache hit” is said to occur if an item, e.g., data, requestedby the processor in the server or a client in a network system, ispresent in the disk cache. When an item, e.g., data, requested by theprocessor in the server or a client in the network system, is notpresent in the cache, a “cache miss” is said to occur. A “cache hitrate” may refer to the rate at which cache hits occur. By improving thecache hit rate, the performance of the system may be improved, i.e.,less data needs to be serviced from the disk.

[0007] One method to improve the performance of a disk cache is commonlyreferred to as the Least Recently Used (LRU) replacement method asillustrated in FIG. 1. The LRU replacement method uses a single stack101 comprising a set of cache entries where each cache entry storesparticular data. As stated above, if an item, e.g., data, requested bythe processor in the server or client in a network system is present inthe cache, a “cache hit” is said to occur. When a cache hit occurs, thecache entry comprising the information, e.g., data, requested moves tothe first stack position as illustrated in FIG. 1. As stated above, ifan item, e.g., data, requested by the processor in the server or clientin a network system is not present in the cache, a “cache miss” is saidto occur. When a cache miss occurs, the requested item is retrieved fromthe disk and then stored in the first stack position as illustrated inFIG. 1. When a new entry is inserted in stack 101, the cache entry inthe last stack position of stack 101 is evicted. The information, e.g.,data, may subsequently be discarded.

[0008] Another method to improve the performance of a disk cache iscommonly referred to as the Segmented LRU (S-LRU) replacement method asillustrated in FIG. 2. The S-LRU replacement method may use two stacks201A-B. Each stack, stack 201A-B, may comprise a set of cache entrieswhere each cache entry stores particular data. When a cache hit occursin the first stack, e.g., stack 201 A, the cache entry comprising theinformation, e.g., data, requested moves up to the first stack positionof the second stack, e.g., stack 201B, as illustrated in FIG. 2. When anew entry is added to stack 201B, the cache entry at the last stackposition of stack 201B is evicted to the first stack position of stack201A. When a new entry is inserted in stack 201A, the cache entry at thelast stack position of stack 201A is evicted. The information, e.g.,data, may subsequently be discarded. When a cache hit occurs in thesecond stack, e.g., stack 201B, the cache entry comprising theinformation, e.g., data, requested moves up to the first stack positionof that stack, e.g., stack 201B, as illustrated in FIG. 2. When a newentry is inserted in stack 201B, the cache entry at the last stackposition of stack 201B is evicted to the first stack position of stack201A. When a new entry is inserted in stack 201A, the cache entry at thelast stack position of stack 201A is evicted. The information, e.g.,data, may subsequently be discarded. When a cache miss occurs, therequested item is retrieved from the disk and then stored in the firststack position of the first stack, e.g., stack 201A, as illustrated inFIG. 2. When a new entry is inserted in stack 201A, the cache entry atthe last stack position of stack 201A is evicted. The information, e.g.,data, may subsequently be discarded.

[0009] Unfortunately, these methods of cache design do not effectivelyconfigure a cache to handle the workload requests efficiently. That is,these methods do not efficiently use memory space thereby improving thecache hit rate since the cache is not designed based on an analysis ofthe workload.

[0010] It would therefore be desirable to develop a cache based on ananalysis of the workload thereby improving performance of the cache,i.e., improving the cache hit rate, using a Least Recently Used(LRU)—Least Frequently Used (LFU) array.

SUMMARY

[0011] The problems outlined above may at least in part be solved insome embodiments by designing a Least Recently Used (LRU)—LeastFrequently Used (LFU) cache array based on an analysis of the workload.

[0012] In one embodiment of the present invention, a method fordesigning a cache may comprise the step of a server in a network system,e.g., file system, database system, receiving requests, e.g., read fromor write to a disk in the server, from one or more clients. Theserequests may form a workload comprising the requests that need to beserviced by the server. A trace may be performed on the workload toprovide information such as the frequency count for each Logical BlockAddress (LBA) referenced in the workload, i.e., the number of times eachparticular LBA was referenced. The trace may then be analyzed bygrouping the LBA's with the same frequency count and determining thenumber of groups counted in the trace. Upon analyzing the trace, anLRU-LFU cache may be designed based on the analysis of the trace. AnLRU-LFU cache may comprise one or more stacks of cache entries where thenumber of stacks corresponds to the number of frequency groups countedin the trace. Each particular stack may then have a length based on thenumber of logical addresses with the same frequency count associatedwith that particular stack. Stacks may be arranged in an array from mostfrequently used to least frequently used. That is, the stack associatedwith the highest frequency count may be located at the highest level ofthe array and the stack associated with the lowest frequency count maybe located at the lowest level of the array. The cache entries in eachparticular stack may be arranged from most recently used to leastrecently used based on a logical time stamp associated with eachparticular cache entry. The logical time stamp may indicate the time theinformation, e.g., data, in the associated cache entry was requested.Upon the storing of a new cache entry in a particular stack, a cacheentry located at the least recently used stack position may be evicted.When the cache entry is evicted, the information, e.g., data, associatedwith the evicted cache entry may be discarded.

[0013] In another embodiment of the present invention, the cache entriesevicted may be stored at the most recently used stack position in thenext higher level stack except if the cache entry is located in thehighest level cache of the cache array. In another embodiment of thepresent invention, the cache entries evicted may be stored at the mostrecently used stack position in the next lower level stack except if thecache entry is located in the lowest level cache of the cache array.

[0014] The foregoing has outlined rather broadly the features andtechnical advantages of the present invention in order that the detaileddescription of the invention that follows may be better understood.Additional features and advantages of the invention will be describedhereinafter which form the subject of the claims of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] A better understanding of the present invention can be obtainedwhen the following detailed description is considered in conjunctionwith the following drawings, in which:

[0016]FIG. 1 illustrates an embodiment of the Least Recently Usedreplacement method for designing a cache;

[0017]FIG. 2 illustrates an embodiment of the Segmented Least RecentlyUsed replacement method for designing a cache;

[0018]FIG. 3 illustrates an embodiment of a network system configured inaccordance with the present invention;

[0019]FIG. 4 illustrates an embodiment of the present invention of aserver;

[0020]FIG. 5 is a flowchart of a method for designing a cache using anLRU-LFU array;

[0021]FIG. 6 illustrates an embodiment of an LRU-LFU cache arrayconfigured in accordance with the present invention;

[0022]FIG. 7 illustrates an embodiment of an LRU-LFU cache comprisingtwo logical portions configured in accordance with the presentinvention;

[0023]FIG. 8 illustrates an embodiment of a template for an LRU-LFUcache array configured in accordance with the present invention;

[0024]FIG. 9 illustrates another embodiment of an LRU-LFU cache arrayconfigured in accordance with the present invention where an evictedcache entry may be stored in the most recently used stack position inthe next higher level stack; and

[0025]FIG. 10 illustrates another embodiment of an LRU-LFU cache arrayconfigured in accordance with the present invention where an evictedcache entry may be stored in the most recently used stack position inthe next lower level stack.

DETAILED DESCRIPTION

[0026] The present invention comprises a system, computer programproduct and method for designing a cache. In one embodiment of thepresent invention, a server in a network system, e.g., file system,database system, may receive requests, e.g., read from or write to adisk in the server, from one or more clients. These requests may form aworkload comprising the requests that need to be serviced by the server.A trace may be performed on the workload to provide information such asthe frequency count for each Logical Block Address (LBA) referenced inthe workload, i.e., the number of times each particular LBA wasreferenced. The trace may then be analyzed by grouping the LBA's withthe same frequency count and determining the number of groups counted inthe trace. Upon analyzing the trace, an LRU-LFU cache may be designedbased on the analysis of the trace. An LRU-LFU cache may comprise one ormore stacks of cache entries where the number of stacks corresponds tothe number of frequency groups counted in the trace. Each particularstack may then have a length based on the number of logical addresseswith the same frequency count associated with that particular stack.Stacks may be arranged in an array from most frequently used to leastfrequency used. That is, the stack associated with the highest frequencycount may be located at the highest level of the array and the stackassociated with the lowest frequency count may be located at the lowestlevel of the array. The cache entries in each particular stack may bearranged from most recently used to least recently used based on alogical time stamp associated with each particular cache entry. Thelogical time stamp may indicate the time the information, e.g., data, inthe associated cache entry was requested. It is noted that even thoughthe following discusses the present invention in connection with a diskcache the present invention may be implemented in any type of cacheincluding a memory cache and a filter cache.

[0027]FIG. 3—Network System

[0028]FIG. 3 illustrates one embodiment of the present invention of anetwork system 300. Network system 300 may comprise one or more clients301A-D configured to send requests to a server 302, e.g., file server,database server, web server. Clients 301A-D may collectively orindividually be referred to as clients 301 or client 301, respectively.It is noted that system 300 may comprise any number of clients 301 andthat FIG. 3 is illustrative. It is further noted that network system 300may be any type of system such as a file system or a database system andthat FIG. 3 is not to be limited in scope to any one particularembodiment.

[0029]FIG. 4—Server

[0030]FIG. 4 illustrates an embodiment of the present invention ofserver 302. Referring to FIGS. 3 and 4, one or more clients 301 mayissue requests to read from or write to a disk 420 in server 302. It isnoted that the embodiment of the present invention is not limited toread and/or write requests but any requests that require service fromserver 302. As stated in the Background Information section, theserequests may form what is commonly referred to as a workload. That is, aworkload may refer to the requests that need to be serviced by server302. In one embodiment, the workload may be managed by a disk adapter418. If these requests in the workload may be serviced by a disk cache460 within disk adapter 418 instead of disk 420, then the data requestedmay be accessed faster. Therefore, it is desirable to optimize the diskcache 460 so that as many requests may be serviced by disk cache 460 aspossible. It is noted that disk cache 460 may reside in other locationsthan disk adapter 418, e.g., disk unit 420, application 450. A methodfor designing a cache, e.g., disk cache 460, with an improvedperformance, i.e., services more requests, using a Least Recently Used(LRU)—Least Frequently Used (LFU) array is described in the descriptionof FIG. 5.

[0031] Referring to FIG. 4, server 302 may further comprise a centralprocessing unit (CPU) 410 coupled to various other components by systembus 412. An operating system 440 runs on CPU 410 and provides controland coordinates the function of the various components of FIG. 4.Application 450, e.g., program for designing a cache, e.g., disk cache460, as described in FIG. 5, runs in conjunction with operating system440 which implements the various functions to be performed byapplication 450. Read only memory (ROM) 416 is coupled to system bus 412and includes a basic input/output system (“BIOS”) that controls certainbasic functions of server 302. Random access memory (RAM) 414, diskadapter 418 and communications adapter 434 are also coupled to systembus 412. It should be noted that software components including operatingsystem 440 and application 450 are loaded into RAM 414 which is thecomputer system's main memory. Disk adapter 418 may be a small computersystem interface (“SCSI”) adapter that communicates with disk units 420,e.g., disk drive. It is noted that the program of the present inventionthat designs a cache, e.g., disk cache 460, as described in FIG. 5 mayreside in disk unit 420 or in application 450. Communications adapter434 interconnects bus 412 with an outside network enabling server 302 tocommunicate with clients 301 or other such systems. Input/Output devicesare also connected to system bus 412 via a user interface adapter 422and a display adapter 436.

[0032] Implementations of the invention include implementations as acomputer system programmed to execute the method or methods describedherein, and as a computer program product. According to the computersystem implementations, sets of instructions for executing the method ormethods are resident in the random access memory 414 of one or morecomputer systems configured generally as described above. Until requiredby server 302, the set of instructions may be stored as a computerprogram product in another computer memory, for example, in disk drive420 (which may include a removable memory such as an optical disk orfloppy disk for eventual use in disk drive 420). Furthermore, thecomputer program product can also be stored at another computer andtransmitted when desired to the user's workstation by a network or by anexternal network such as the Internet. One skilled in the art wouldappreciate that the physical storage of the sets of instructionsphysically changes the medium upon which it is stored so that the mediumcarries computer readable information. The change may be electrical,magnetic, chemical or some other physical change.

[0033]FIG. 5—Method for Designing a Cache

[0034]FIG. 5 is a flowchart of one embodiment of the present inventionof a method 500 for designing a cache, e.g., disk cache 460, using aLeast Recently Used (LRU)—Least Frequently Used (LFU) array. As statedin the Background Information section, prior art methods of designingcaches do not effectively design a cache to handle workload requestsefficiently. That is, prior art cache design methods do not designcaches that efficiently use memory space since the cache is not designedbased on an analysis of the workload. It would therefore be desirable todevelop a cache based on an analysis of the workload thereby improvingperformance of the cache, i.e., improving the cache hit rate using aLeast Recently Used (LRU)—Least Frequently Used (LFU) array. Method 500is a method for designing a cache that uses an LRU-LFU array.

[0035] In step 501, server 302 may be configured to receive requestsfrom one or more clients 301 forming a workload. The workload maycomprise requests to read from and/or write to disk 420 of server 302.It is noted that the workload may comprise any number of requests. It isfurther noted that in one embodiment, the workload, i.e., requeststream, may be managed by disk adapter 418. It is further noted that theembodiment of the present invention is not limited to read and/or writerequests but any requests that require service from server 302.

[0036] In step 502, a trace may be performed on the request stream fromclients 301, i.e., a trace may be performed on the workload. In oneembodiment, the trace may be performed on the request stream in diskadapter 418. In one embodiment, the trace may provide information as tothe frequency count for each particular Logical Block Address (LBA)referenced in the workload, i.e., the number of times each particularLogical Block Address (LBA) was referenced. In step 503, the trace maybe analyzed by grouping LBA's with the same frequency count anddetermining the number of groups counted as illustrated in the exemplaryTable 1 below. TABLE 1 Number of Different Addresses in Trace forFrequency Each Particular Frequency Count Count Total Number of Requests1 9521 9521 2 2369 4738 3 565 1695 4 287 1148 5 210 1050 6 237 1422 7507 3549 8 1018 8144 9 305 2745 10 225 2250 11 104 1144 12 70 840 13 26338 14 39 546 15 305 4575 16 306 4896 17 12 204 18 1 18 19 3 57 20 1 2022 1 22 23 1 23 24 2 48 27 1 27 32 7 224 49244

[0037] Table 1 above illustrates an example of a trace conducted on49,244 requests in a particular workload. The first column of Table 1indicates the frequency count measured for each particular group. Thesecond column of Table 1 indicates the number of different logicaladdresses with the same frequency count. The third column of Table 1indicates the total number of requests in the trace for each particularfrequency count by multiplying the frequency count for that group withthe number of different logical addresses with that particular frequencycount. Table 1 indicates that there were twenty-five different frequencycount groups. Table 1 further indicated that no logical address wasreferenced more than thirty-two times and that not logical address wasreferenced with a frequency count of 21, 25, 26, 28, 29, 30 or 31 times.In a cache memory, the longer that logical addresses with frequencycounts two or greater remain in the cache, the higher a hit rate may beachieved. The higher the hit rate the greater the performance of thecache. Method 500 is a method that improves the cache hit rate bydesigning a cache based upon the analysis of the trace in step 503 asexplained in greater detail below.

[0038] In step 504, an LRU-LFU cache array may be designed based on theanalysis of the trace in step 503. A basic structure of an LRU-LFU cachearray based on the analysis of the trace as illustrated in Table 1 isdepicted in FIG. 6. FIG. 6 illustrates an embodiment of an LRU-LFU cachearray 600 based on the analysis of the trace as illustrated in Table 1.LRU-LFU cache array 600 comprises a plurality of stacks 601A-601Ycorresponding to the number of frequency count groups in Table 1, e.g.,twenty-five different frequency groups in Table 1. That is, each stackof cache array 600, stacks 601A-601Y, is associated with a particularfrequency count group. For example, stack 601A is associated with thefrequency count group of one, i.e., associated with logical addressesreferenced once. Stack 601B is associated with the frequency count groupof two, i.e., associated with logical addresses referenced twice. Stack601C is associated with the frequency count group of three, i.e.,associated with logical addresses referenced three times. Stack 601X isassociated with the frequency count group of thirty-two, i.e.,associated with logical addresses referenced thirty-two times. Stacks601A-601Y may collectively or individually be referred to as stacks 601or stack 601, respectively. It is noted that LRU-LFU cache array 600 maycomprise one or more stacks 601 which are dependent upon the number offrequency count groups indicated in the trace analyzed in step 503 andthat FIG. 6 is illustrative.

[0039] Referring to FIG. 6, the length of each particular stack 601corresponds to the number of logical addresses with the same frequencycount. For example, there were 9,521 different logical addresses with afrequency count of 1 as indicated in Table 1. Subsequently, stack 601Awhich is a stack 601 associated with a frequency count of 1 has a lengthof 9,521.

[0040] Cache array 600 may comprise two logical portions, e.g., datastorage area 701 and cache directory 702 as illustrated in FIG. 7. FIG.7 illustrates an embodiment of present invention of cache array 600comprising two logical portions. It is noted that cache array 600 maycomprise a different number of logical portions and that FIG. 7 isillustrative. Referring to FIG. 7, a first logical portion is a datastorage area 701 where data storage area 701 comprises a set of cacheentries where each cache entry stores particular data. A second logicalportion is a cache directory 702 storing the logical base addressesassociated with the cache entries in data storage area 701. Cachedirectory 702 may further be configured to store a logical time stampassociated with each cache entry in data storage area 701 indicating thetime the information, e.g., data, in the associated cache entry wasrequested. Cache directory 702 may further be configured to store thefrequency count associated with each cache entry in cache array 600where the frequency count indicates the number of times the information,e.g., data, in the associated cache entry was requested.

[0041] Referring to FIG. 6, the cache entries in each particular stack601, e.g., stacks 601A-X, may be ordered within stack 601 from mostrecently used to least recently used based on the logical time stamps ofthe cache entries. That is, the cache entry whose logical time stampindicates the most recent time entry of all the cache entries in stack601 is placed in the first stack position in stack 601. The cache entrywhose logical time stamp indicates the last time entry of all the cacheentries in stack 601 is placed in the last stack position in stack 601.

[0042] Referring to FIG. 6, stacks 601A-X may be ordered from mostfrequently used to least frequently used. For example, stack 601A islocated on the lowest level of the array since the frequency count groupassociated with stack 601A is one. Stack 601X is located on the highestlevel of the array since the frequency count group associated with stack601X is thirty-two which corresponds to the highest number of times oneor more logical addresses were referenced in the workload. It is notedthat cache array 600 may comprise one or more stacks 601 based on thenumber of frequency count groups identified in the analysis of the tracein step 503. For example, if there were three frequency count groupsidentified in the analysis of the trace in step 503, then there would bethree stacks 601 in cache array 600. It is further noted that more thanone frequency count group may be grouped in a particular stack 601. Forexample, a developer may establish that stack 601A is associated with afrequency count of Co, e.g., two, and stack 601B is associated with afrequency count of Cl, e.g., five. That is, stack 601A may store cacheentries associated with logical addresses that have been referenced Co,e.g., two, or less times. Stack 601B may store cache entries associatedwith logical addresses that have been referenced greater than thefrequency count, e.g., Co, associated with the next lower level stack601, e.g., stack 601A, and less than or equal to Cl, e.g., five, times.A generic template for an LRU-LFU cache array 800 illustrating suchdesign constraints by a developer is illustrated in FIG. 8.

[0043]FIG. 8 illustrates an embodiment of the present invention of ageneric template for an LRU-LFU cache array 800. Cache array 800 maycomprise one or more stacks 801, e.g., stacks 801A-N, where the one ormore stacks 801 are ordered based on the frequency count. For example,stack 801A is associated with a frequency count group of Co. That is,the logical addresses associated with each of the cache entries in stack801A have been referenced C₀ or less times. Stack 801B is associatedwith a frequency count group of C₁. That is, the logical addressesassociated with each of the cache entries in stack 801B have beenreferenced greater than the frequency count, e.g., C₀, associated withthe next lower level stack 801, e.g., stack 801A, and less than or equalto C₁ times. Stack 801N is associated with a frequency count group ofC_(N). That is, the logical addresses associated with each of the cacheentries in stack 801N have been referenced greater than the frequencycount associated with the next lower level stack 801 and less than orequal to C_(N) times.

[0044]FIG. 8 further illustrates that cache array 800 may be volatile.That is, the cache entries in the one or more stacks 801 of cache array800 may vary when a cache hit or cache miss occurs. FIG. 8 furtherillustrates that upon the storing of a new cache entry in a particularstack 801 at the most recently used stack position a cache entry at theleast recently used stack position in that particular stack 801 may beevicted. When the cache entry in the least recently used stack positionis evicted, the information stored in the least recently used stackposition may be discarded.

[0045] When an item, e.g., data, requested is present in a particularcache entry a “cache hit” is said to occur. When a cache hit occurs in aparticular stack 801, e.g., stack 801A, the frequency count associatedwith that cache entry is updated, i.e., increased by one, in the cachedirectory. If the updated frequency count associated with thatparticular cache entry subsequently increases in number to the frequencycount, e.g., C₁, associated with the next higher level stack 801, e.g.,stack 801B, then that particular cache entry may be stored in the mostrecently used stack position in the next higher level stack 801, e.g.,stack 801B. Upon storing the particular cache entry in the most recentlyused stack position in the next higher level stack 801, e.g., stack801B, the cache entry in the least recently used stack position in thenext higher level stack 801, e.g., stack 801B, may be evicted. If theupdated frequency count associated with that particular cache does notincrease in number to the frequency count, e.g., C₁, associated with thenext higher level stack 801, e.g., stack 801B, then that particularcache entry may be stored in the most recently used stack position inits particular stack 801, e.g., stack 801A.

[0046] When an item, e.g., data, requested is not present in aparticular cache entry a “cache miss” is said to occur. When a cachemiss occurs, the requested item, e.g., data, may be retrieved from disk420 and then stored in the most recently used stack position of thelowest level stack, e.g., stack 801A, as illustrated in FIG. 8. When anew entry is inserted in stack 801A, the cache entry in the leastrecently used stack position of stack 801A may be evicted. Theinformation, e.g., data, in the cache entry in the least most recentlyused stack position may subsequently be discarded.

[0047] In another embodiment, the cache entry in a particular stack 801evicted may be stored at the most recently used stack position in thenext higher level stack 801 in the LRU-LFU cache array as illustrated inFIG. 9. FIG. 9 illustrates an embodiment of the present invention of acache array 900 that is the same as cache array 900 except that thecache entries evicted in a particular stack 801 may be stored at themost recently used stack position in the next higher level stack 801except if the cache entry evicted is located in the highest level stack801 of the cache array. For example, a cache entry evicted in the leastrecently used stack position in the lowest level stack 801, e.g., stack801A, of cache array 900 may be stored in the most recently used stackposition in the next higher level stack 801, e.g., stack 801B. The cacheentry evicted in the least recently used stack position in 801B of cachearray 900 may be stored in the most recently used stack position in thenext higher level stack 801, e.g., stack 801C. The information in thecache entry evicted in the least recently used stack position in thehighest level stack 801, e.g., stack 801N, of cache array 900 may bediscarded since there are no more stacks 801 located above stack 801N incache array 900.

[0048] In another embodiment, the cache entry in a particular stack 801evicted may be stored at the most recently used stack position in thenext lower level stack 801 in the LRU-LFU cache array as illustrated inFIG. 10. FIG. 10 illustrates an embodiment of the present invention of acache array 1000 that is the same as cache array 1000 except that thecache entries evicted in a particular stack 801 may be stored at themost recently used stack position in the next lower level stack 801except if the cache entry evicted is located in the lowest level stack801 in the cache array. For example, a cache entry evicted in the leastrecently used stack position in the highest level stack 801, e.g., stack801N, of cache array 1000 may be stored in the most recently used stackposition in the next lower level stack 801, e.g., stack 801B. The cacheentry evicted in the least recently used stack position in 801B of cachearray 1000 may be stored in the most recently used stack position in thenext lower level stack 801, e.g., stack 801A. The information in thecache entry evicted in the least recently used stack position in thelowest level stack 801, e.g., stack 801A, of cache array 1000 may bediscarded since there are no more stacks 801 located below stack 801A incache array 1000.

[0049] It is noted that for simplicity the features, e.g., evictingcache entries in the least recently used stack position, discussed inFIGS. 8-10 in relation to cache arrays 800, 900, 1000, respectively,were not explicitly illustrated in FIG. 6 in relation to cache array 600but are apparent to one of ordinary skill in the art.

[0050] Although the system, computer program product and method aredescribed in connection with several embodiments, it is not intended tobe limited to the specific forms set forth herein, but on the contrary,it is intended to cover such alternatives, modifications, andequivalents, as can be reasonably included within the spirit and scopeof the invention as defined by the appended claims. It is noted that theheadings are used only for organizational purposes and not meant tolimit the scope of the description or claims.

1. A method for designing a cache comprising the steps of: receivingrequests forming a workload; performing a trace of said workload;analyzing said trace of said workload; and designing one or more stacksof cache entries based on said analysis of said trace of said workload.2. The method as recited in claim 1 further comprising the step of:designing a length of each of said one or more stacks of said cacheentries based on said analysis of said trace of said workload.
 3. Themethod as recited in claim 1, wherein said requests that form saidworkload are requests to access a disk.
 4. The method as recited inclaim 1, wherein said requests are issued from one or more clients in anetwork system to a network server, wherein said cache is associatedwith said network server.
 5. The method as recited in claim 1, whereinsaid cache comprises a plurality of logical sections, wherein one ofsaid plurality of logical sections comprises information, wherein one ofsaid plurality of logical sections comprises a cache directory.
 6. Themethod as recited in claim 5, wherein said cache directory in said cachecomprises a logical based address associated with each cache entry insaid cache.
 7. The method as recited in claim 5, wherein said cachedirectory in said cache comprises a logical time stamp associated witheach cache entry in said cache.
 8. The method as recited in claim 5,wherein said cache directory in said cache comprises a frequency countassociated with each cache entry in said cache.
 9. The method as recitedin claim 8, wherein said frequency count is a number of requests to aparticular cache entry.
 10. The method as recited in claim 8, whereinsaid one or more stacks are designed in an array based on said frequencycount of said cache entries.
 11. The method as recited as recited inclaim 10, wherein each of said one or more stacks comprises cacheentries associated with a particular frequency count.
 12. The method asrecited in claim 7, wherein each of said one or more one or more stackscomprises cache entries ordered from most recently used to leastrecently used based on said logical time stamps of said cache entries.13. The method as recited in claim 12, wherein a cache entry at a leastrecently used stack position in a particular stack is evicted upon thestoring of a new cache entry at a most recently used stack position insaid particular stack.
 14. The method as recited in claim 13, whereininformation in said evicted cache entry is discarded.
 15. The method asrecited in claim 13, wherein said evicted cache entry is stored at saidmost recently used stack position of a next lower level stack exceptwhen said particular stack is a lowest level stack.
 16. The method asrecited in claim 13, wherein said evicted cache entry is stored at saidmost recently used stack position of a next higher level stack exceptwhen said particular stack is a highest level stack.
 17. The method asrecited in claim 13, wherein said new cache entry is stored at said mostrecently used stack position in said particular stack upon a cache miss.18. A computer program product having computer readable medium havingcomputer program logic recorded thereon for designing a cache,comprising: programming operable for receiving requests forming aworkload; programming operable for performing a trace of said workload;programming operable for analyzing said trace of said workload; andprogramming operable for designing one or more stacks of cache entriesbased on said analysis of said trace of said workload.
 19. The computerprogram product as recited in claim 18 further comprises: programmingoperable for designing a length of each of said one or more stacks ofsaid cache entries based on said analysis of said trace of saidworkload.
 20. The computer program product as recited in claim 18,wherein said requests that form said workload are requests to access adisk.
 21. The computer program product as recited in claim 18, whereinsaid requests are issued from one or more clients in a network system toa network server, wherein said cache is associated with said networkserver.
 22. The computer program product as recited in claim 18, whereinsaid cache comprises a plurality of logical sections, wherein one ofsaid plurality of logical sections comprises information, wherein one ofsaid plurality of logical sections comprises a cache directory.
 23. Thecomputer program product as recited in claim 22, wherein said cachedirectory in said cache comprises a logical based address associatedwith each cache entry in said cache.
 24. The computer program product asrecited in claim 22, wherein said cache directory in said cachecomprises a logical time stamp associated with each cache entry in saidcache.
 25. The computer program product as recited in claim 22, whereinsaid cache directory in said cache comprises a frequency countassociated with each cache entry in said cache.
 26. The computer programproduct as recited in claim 25, wherein said frequency count is a numberof requests to a particular cache entry.
 27. The computer programproduct as recited in claim 25, wherein said one or more stacks aredesigned in an array based on said frequency count of said cacheentries.
 28. The computer program product as recited as recited in claim27, wherein each of said one or more stacks comprises cache entriesassociated with a particular frequency count.
 29. The computer programproduct as recited in claim 24, wherein each of said one or more one ormore stacks comprises cache entries ordered from most recently used toleast recently used based on said logical time stamps of said cacheentries.
 30. The computer program product as recited in claim 29,wherein a cache entry at a least recently used stack position in aparticular stack is evicted upon the storing of a new cache entry at amost recently used stack position in said particular stack.
 31. Thecomputer program product as recited in claim 30, wherein information insaid evicted cache entry is discarded.
 32. The computer program productas recited in claim 30, wherein said evicted cache entry is stored atsaid most recently used stack position of a next lower level stackexcept when said particular stack is a lowest level stack.
 33. Thecomputer program product as recited in claim 30, wherein said evictedcache entry is stored at said most recently used stack position of anext higher level stack except when said particular stack is a highestlevel stack.
 34. The computer program product as recited in claim 30,wherein said new cache entry is stored at said most recently used stackposition in said particular stack upon a cache miss.
 35. A systemcomprising: one or more clients; a server coupled to said one or moreclients, wherein said server comprises: a processor; a memory unitoperable for storing a computer program operable for designing a cache;and a bus system coupling the processor to the memory, wherein thecomputer program is operable for performing the following programmingsteps: receiving requests forming a workload; performing a trace of saidworkload; analyzing said trace of said workload; and designing one ormore stacks of cache entries based on said analysis of said trace ofsaid workload.
 36. The system as recited in claim 35, wherein thecomputer program product is further operable to perform the programmingstep: designing a length of each of said one or more stacks of saidcache entries based on said analysis of said trace of said workload. 37.The system as recited in claim 35, wherein said requests that form saidworkload are requests to access a disk.
 38. The system as recited inclaim 35, wherein said requests are issued from said one or more clientsto said server.
 39. The system as recited in claim 35, wherein saidcache comprises a plurality of logical sections, wherein one of saidplurality of logical sections comprises information, wherein one of saidplurality of logical sections comprises a cache directory.
 40. Thesystem as recited in claim 39, wherein said cache directory in saidcache comprises a logical based address associated with each cache entryin said cache.
 41. The system as recited in claim 39, wherein said cachedirectory in said cache comprises a logical time stamp associated witheach cache entry in said cache.
 42. The system as recited in claim 39,wherein said cache directory in said cache comprises a frequency countassociated with each cache entry in said cache.
 43. The system asrecited in claim 42, wherein said frequency count is a number ofrequests to a particular cache entry.
 44. The system as recited in claim42, wherein said one or more stacks are designed in an array based onsaid frequency count of said cache entries.
 45. The system as recited asrecited in claim 44, wherein each of said one or more stacks comprisescache entries associated with a particular frequency count.
 46. Thesystem as recited in claim 41, wherein each of said one or more one ormore stacks comprises cache entries ordered from most recently used toleast recently used based on said logical time stamps of said cacheentries.
 47. The system as recited in claim 46, wherein a cache entry ata least recently used stack position in a particular stack is evictedupon the storing of a new cache entry at a most recently used stackposition in said particular stack.
 48. The system as recited in claim47, wherein information in said evicted cache entry is discarded. 49.The system as recited in claim 47, wherein said evicted cache entry isstored at said most recently used stack position of a next lower levelstack except when said particular stack is a lowest level stack.
 50. Thesystem as recited in claim 47, wherein said evicted cache entry isstored at said most recently used stack position of a next higher levelstack except when said particular stack is a highest level stack. 51.The system as recited in claim 47, wherein said new cache entry isstored at said most recently used stack position in said particularstack upon a cache miss.